1. Field of the Invention
The present invention relates to a protection circuit, and more particularly to an electrostatic discharge protection circuit.
2. Description of Related Art
Generally speaking, a lateral double diffused NMOSFET (LDNMOS) is used to realize the ESD protection circuit to provide electrostatic protection for power integrated circuit (IC), as shown in FIG. 1. FIG. 1 is a schematic view of a conventional ESD protection circuit and a wiring mode thereof. In FIG. 1, the mark 101 denotes a part of the circuit in an IC chip, and the mark 102 denotes an output pad of an internal circuit signal. The internal circuit of the chip may transmit signals through the output pad 102 of the internal circuit signal. Definitely, the static electricity causes impact on the internal circuit of the chip through the output pad 102 of the internal circuit signal. The mark 103 denotes the ESD protection circuit realized by an LDNMOS transistor 104. It can be known from the figure that the drain 105 of the LDNMOS transistor 104 is connected to the output pad 102 of the internal circuit signal, and the gate, source, and P-body of the LDNMOS transistor 104 are connected to the common ground potential GND.
When the output pad 102 of the internal circuit signal is impacted by a negative ESD, the drain 105 also assumes a negative potential level. The potential level of the drain 105 is lower than that of the P-body of the LDNMOS transistor 104. A PN junction between the P-body and the drain 105 of the LDNMOS transistor 104 is in the forward-bias state, so as to quickly conduct a negative ESD current into the common ground potential GND, and to prevent the internal circuit of the chip from being impacted by the negative ESD. However, when the output pad 102 of the internal circuit signal is impacted by a positive ESD, the potential level of the drain 105 will be higher than that of the P-body of the LDNMOS transistor 104, and the PN junction between the P-body and the drain 105 of the LDNMOS transistor 104 is in the reverse-bias state. Thus, the quick discharge cannot be achieved, and the internal circuit of the chip cannot be effectively protected.
FIG. 2 is a schematic cross-sectional view of a structure of the LDNMOS transistor. In this figure, N+ denotes an N-type highly-doped region, and P+ denotes a P-type highly-doped region. In the two N-type highly-doped regions, the N-type highly-doped region of the drain 201 is located in an N-drift region 209, and the N-type highly-doped region of the source 202 is located in the P-body 210. Marks 203-206 denote a drain contact, a polysilicon gate contact, a source contact, and a P-body contact in sequence. In addition, the mark 207 denotes a polysilicon gate, the mark 208 denotes a field oxide, the mark 211 denotes a high-voltage deep-N-well, and a mark 212 denotes a P-substrate.
FIG. 3 is a cross-sectional diagram of an equivalent circuit of the LDNMOS transistor 104 of the ESD protection circuit 103 in FIG. 1. An N-doped region is composed of the N-type highly-doped region 201 of the drain, the N-drift region 209, and the high-voltage deep-N-well 211, a P-doped region is composed of the P-type highly-doped region and the P-body 210, and the N-type highly-doped region 202 of the source are shown in this figure, and may form a parasitic NPN bipolar junction transistor (parasitic NPN transistor) 301. In addition, the mark 302 denotes a parasitic resistor between a base of the parasitic NPN transistor 301 and the P-body contact 206.
As shown in FIG. 3, when the output pad 102 of the internal circuit signal is impacted by a negative ESD, the P-body 210 of the LDNMOS transistor 104 is connected to the common ground potential through the P-body contact 206, while the N-doped region is composed of the N-type highly-doped region 201 of the drain, the N-drift region 209, and the high-voltage deep-N-well 211, and the N-doped region is connected to a negative ESD through the drain contact 203 and the output pad 102 of the internal circuit signal successively. Therefore, a PN junction between the P-body 210 and the N-doped region is in the forward-bias state. As the P-substrate 212 is connected to the common ground potential, a PN junction between the P-substrate 212 and the N-doped region is also in the forward-bias state, so that the discharge may be achieved through the forward-bias PN junction. However, when the output pad 102 of the internal circuit signal is impacted by the positive ESD, the high current pulse injected in a short time must be discharged by triggering the parasitic NPN transistor 301 of the LDNMOS transistor 104 to enter a snapback breakdown state. The LDNMOS transistor is a kind of the high-voltage transistor, and has a high breakdown voltage. A length of a channel of the high-voltage transistor element is greater than that of a channel of a low-voltage transistor. Thus, when the ESD protection circuit 103 realized by the LDNMOS transistor 104 is impacted by the positive ESD, it is quite difficult to quickly trigger the parasitic NPN transistor 301 to enter the snapback breakdown state for discharging. As a result, the internal circuit of the chip may be burnt before the ESD protection circuit 103 is fully started.
It can be known from the above that when the power IC chip adopts the ESD protection circuit as described above, it is difficult to quickly trigger the parasitic NPN transistor of the LDNMOS transistor to enter the snapback breakdown state. Therefore, a positive ESD path cannot be formed rapidly, which results in a weak capability of power IC chip to withstand ESD.